1. Field of the Invention
The present invention relates to a power supply voltage control apparatus that controls power supply voltage of a semiconductor integrated circuit apparatus such as an LSI (Large Scale Integration)
2. Description of the Related Art
In recent years, as important methods for reducing power consumption of the semiconductor integrated circuit, methods of changing power supply voltage according to clock frequencies are well-known. However, when the accuracy of power supply voltage setting is coarse, or, when a power supply voltage setting circuit is temperature dependant, errors in circuit operation may occur as a result of timing errors by reducing power supply voltage too low. Further, there are also cases where timing errors may occur as a result of decrease of the driving performance of a MOS transistor due to temperature fluctuation, and may lead errors in circuit operation.
With regards to this problem, conventionally, a voltage generating circuit technology is disclosed that is capable of generating the minimum required operation power supply voltage in a predetermined clock frequency. For example, as shown in FIG. 10, Patent Document 1 (Japanese Patent Application Laid-Open No. Hei. 9-285109) discloses a semiconductor apparatus having: a logic circuit that operates using first power supply voltage; a voltage control oscillator section that generates a clock signal of a frequency corresponding to second power supply voltage; a phase comparator that compares phases of the clock signal and a reference clock signal; a low pass filter section that smoothes an input signal using an integrating circuit; a charge pump section that charges and discharges the low pass filter section using the result of the phase comparison; and an internal power supply voltage generating section that generates the first power supply voltage of a level corresponding to output of the low pass filter section, wherein the first and second power supply voltages causing the logic circuit and the clock generating section to operate are shared and supplied from the power supply voltage generating section.
Further, as shown in FIG. 11, Patent Document 2 (Japanese Patent Application Laid-Open No. Hei. 10-49242) discloses, in place of the voltage control oscillator section of Patent Document 1, a power supply generating circuit that performs phase comparison between a clock signal subjected to gate delay at a voltage control delay circuit and an original clock signal, generates a voltage signal using an integrator and a buffer, feeds this back to the voltage control delay circuit as operating power supply voltage, and generates internal power supply voltage using the buffer and PchMOS transistor.
Further, as shown in FIG. 12, in order to provide versatility to the voltage control delay circuit having various delay values in Patent Document 2, Patent Document 3 (Japanese Patent Application Laid-Open No. 2002-100967) discloses a power supply voltage control apparatus provided with an input signal generating circuit that is capable of changing, upon generation of a reference signal inputted from a clock signal to a delay detection circuit and an input signal inputted to a voltage control delay circuit, a phase difference between both signals according to a control signal.
Moreover, as shown in FIG. 13, Patent Document 4 (Japanese Patent Application Laid-Open No. 2000-216337) discloses a power supply voltage control apparatus having: a semiconductor circuit; a replica circuit that monitors delay time of a critical path of the semiconductor circuit; a control circuit that sets a level control signal so that an initial value of power supply voltage becomes a minimum limit power supply voltage value where the semiconductor circuit is capable of operating properly, and setting the level control signal after start-up so as to obtain the power supply voltage value based on a monitor apparatus of the replica circuit; and a power supply voltage generating circuit that generates a power supply voltage according to the level control signal and supplying the voltage to the semiconductor circuit and replica circuit, and thereby enabling convergence time and stable operation upon start up of the power supply.
However, the conventional power supply voltage control apparatuses have the following problems.
The apparatus disclosed in Patent Document 1 sets a period of the reference clock signal inputted to the phase comparator as, for example, one period of the system clock signal. Further, the voltage control oscillator circuit is configured with a fixed number of stages of inverter circuits and critical path replicas, and therefore the period of the clock signal outputted from the voltage control oscillator circuit is equal to the period of the reference clock signal regardless of the frequency of the reference clock signal.
Similarly, the apparatuses disclosed in Patent Documents 2 and 4 set a period of the reference clock signal inputted to the phase comparator as, for example, one period of the system clock signal as with Patent Document 1. Further, the voltage control delay circuit is configured with a fixed number of stages of inverter circuits, and therefore a delay value generated by the voltage control delay circuit is equal to one period of the reference clock signal regardless of the frequency of the reference clock signal.
However, the power supply voltage control circuit takes a certain amount of time from when the power supply voltage is applied and a lag of phase or frequency between the clock output signal of the voltage control oscillator circuit and the reference clock signal is detected till when control actually operates and corrected power supply voltage is applied, and therefore the power supply voltage fluctuates. Moreover, the fluctuation value of the power supply voltage is substantially fixed regardless of the level of the power supply voltage. Therefore, fluctuation values of a maximum system clock frequency where normal operation is possible at the internal circuit with respect to the fluctuation value of the supply power voltage when the supply voltage is small and a clock frequency of the voltage control oscillator circuit, are larger than a fluctuation value of the respective clock frequencies with respect to the fluctuation value of the power supply voltage when the power supply voltage is large.
The reason for this is that the respective clock frequencies are substantially decided by the driving performance of the MOS transistor—the drain current—, and proportional to the square of a value in which the threshold voltage is subtracted from the gate voltage as expressed by the following equation.IDS=α(VGS−Vt)2  (1)
For example, when MOS transistor threshold voltage is 0.5V and a power supply voltage fluctuation value is 0.05V, drain current ratio is 1.07 times between power supply voltages of 2.0V and 2.05V, but between power supply voltages of 1.0V and 1.05V, the drain current ratio becomes 1.21 times.
Therefore, the first problem is that, though it is necessary to change a setting margin of a period of a clock signal outputted from the voltage control oscillator circuit or a delay value generated by the voltage control delay circuit and a period of the reference clock signal with respect to the minimum power supply voltage corresponding to the system clock frequency, Patent Documents 1, 2 and 4 cannot be compatible with this, since the setting margin is fixed.
Further, the apparatus of Patent Document 3 incorporates an input signal generating circuit capable of, when the reference signal and input signal are generated from the inputted clock signal, changing a phase difference between both signals according to a control signal. However, the input signal generating circuit is shared with a monitor circuit having various delay values compatible with functions of the semiconductor circuit, and does not function for changing the clock period setting margin according to the above-described system clock frequency. Further, the input signal generating circuit is configured with a PLL (Phase-Locked Loop) and selector, and therefore the problem arises that circuit scale increases substantially.
The apparatus of Patent Document 4 sets the level control signal so that the initial value becomes a start-up minimum power supply voltage, and, upon start-up of the semiconductor circuit, time for the power supply voltage to converge to an optimum value can be reduced However, the setting of the level control signal is only considered upon start-up of the power supply, and therefore the apparatus cannot be compatible with switching of a plurality of system clock frequencies. Namely, the second problem is that, when the system clock frequency is changed from a high frequency to a low frequency, first, the system clock frequency changes, and the power supply voltage is adjusted to be small according to this frequency, but, when the change in frequency is large, the change in power supply voltage also becomes large, and it takes a great deal of time to converge the power supply to the minimum power supply voltage for normal operation. Further, when the system clock frequency is changed from a low frequency to a high frequency, if the system clock frequency increases before the power supply voltage increases, a problem of inviting errors in the internal circuit operation arises.